The subject invention pertains generally to electronic digital binary counters and in particular to a class of counters commonly referred to as pseudo-random.
As is well known to those familiar with electronic counters, pseudo-random counters which comprise a plurality of flip-flop stages arranged to function as a shift register afford major advantages for integrated circuit designs which greatly outweigh the pseudo-random sequential binary output obtained from any sequential counting segment. Specifically, the absence of the plethora of gates and associated leads required for interconnecting the various stages of other types of conventional counters, particularly when there are numerous stages, affords a neat and compact topological integrated circuit layout which greatly enhances miniaturization and consequently design attractiveness. Unfortunately, the attractiveness of pseudo-random counters for integrated circuit design is somewhat undermined by their inability to count in more than one direction, thus limiting versatility by precluding use as an up/down counter.
With the foregoing in mind, it is a primary object of the present invention to provide a new and improved pseudo-random counter.
It is a further object of the present invention to provide such a pseudo-random counter which is bidirectional, viz. capable of counting in two directions, either to the left or to the right.
It is still a further object of the present invention to provide such counting bidirectionality through the use of two bit streams which are so related that the same binary output is obtained when counting forward in one direction as would have been obtained by counting backward in the opposite direction.
The foregoing objects as well as others, and the means by which they are achieved through the present invention may best be appreciated by referring to the Detailed Description of the Preferred Embodiment which follows hereinafter together with the appended drawings.